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Cypress Semiconductor /psoc63 /CSD0 /REFGEN

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Interpret as REFGEN

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (OFF)REFGEN_EN 0 (BYPASS)BYPASS 0 (VDDA_EN)VDDA_EN 0 (RES_EN)RES_EN 0GAIN0VREFLO_SEL0 (VREFLO_INT)VREFLO_INT

REFGEN_EN=OFF

Description

Reference Generator configuration

Fields

REFGEN_EN

Reference Generator Enable

0 (OFF): Disable Reference Generator

1 (ON): On, regular operation. Note that CONFIG.LP_MODE determines the power mode level
BYPASS

Bypass selected input reference unbuffered to Vrefhi
VDDA_EN

Close Vdda switch to top of resistor string (or Vrefhi?)
RES_EN

Resistor string enable; 0= open switch on top of the resistor string (Vreflo=Vssa)
GAIN

Select resistor string tap for feedback, 0= minimum vout, 31= maximum vout = vrefhi -> gain=1 (only works if the resistor string is enabled; RES_EN=1)
VREFLO_SEL

Select resistor string tap for Vreflo/Vreflo_int, 0= minimum vout, 31= maximum vout = vrefhi (only works if the resistor string is enabled; RES_EN=1)
VREFLO_INT

Ouput the resistor string tap either to Vreflo (0) or Vreflo_int (1).

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data